Multilevel MPSoC Performance Evaluation, New ISSPT Model

To deploy the enormous hardware resources available in Multi-Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, Design Space Exploration (DSE) methods are needed to assess the different design alternatives. In this paper, we present a platform that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of Instruction Set simulation (ISS) level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin. Keyword: multiprocessor systems, estimation of performance, MPSoC, TLM, SystemC, ISS, CABA, priority management Copyright © 2015 Institute of Advanced Engineering and Science. All rights reserved.